Saturday, January 10, 2026

Building a virtio-serial FPGA device (Part 4): Virtqueue processing

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This is the fourth post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we'll lo...

Building a virtio-serial FPGA device (Part 6): Writing the RISC-V firmware

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This is the final post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we'll l...

Building a virtio-serial FPGA device (Part 5): UART receiver and transmitter

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This is the fifth post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we'll l...

Building a virtio-serial FPGA device (Part 3): virtio-serial device design

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This is the third post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we'll l...

Building a virtio-serial FPGA device (Part 2): MMIO registers, DMA, and interrupts

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This is the second post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we...

Building a virtio-serial FPGA device (Part 1): Overview

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This is a the first post in a series about building a virtio-serial device in Verilog for a Field Programmable Gate Array (FPGA) developme...
Thursday, December 11, 2025

What's new in VIRTIO 1.4

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With the VIRTIO 1.4 specification for I/O devices expected to be published soon, here are the most prominent changes. For more fine...